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vishay siliconix si9118, si9119 document number: 70815 s11-0975?rev. e, 16-may-11 www.vishay.com 1 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 programmable duty cycle controller features ? 10 to 200 v input range ? current-mode control ? internal start-up circuit ? buffer slope compensation voltage ? soft-start ? 2.7 mhz error amp ? 500 ma output drive current ? light load frequency fold-back ? low quiescent current ? programmable maximum duty cycle, with 80 % as default description the si9118/si9119 are a b ic/dmos current-mode pulse width modulation (pwm) controller ics for high-frequency dc/dc converters. single-ended topologies (forward and flyback) can be implemented at frequencies up to 1 mhz. the controller operates in co nstant frequency mode during the full load and automatically switches to pulse skipping mode under light load to maintain high efficiency throughout the full load range. the maximum duty cycle is easily programmed with a resistor divider for optimum control. the push-pull output driver provides high-speed switching to external mospower devices large enough to supply 50 w of output power. shoot-through current for internal push-pull stage is almost eliminated to minimize quiescent supply current. the push-pull output driver provides high-speed switching to external mospower devices large enough to supply 50 w of output power. shoot-through current for internal push-pull stage is almost eliminated to minimize quiescent supply current. the high-voltage dmos transisto r permits direct operation from bus voltages of up to 2 00 v. other features include a 1.5 % accurate voltage reference, 2.7 mhz bandwidth error amplifier, standby mode, soft -start and undervoltage lockout circuits. the si9118/si9119 are available in both standard and lead (pb)-free packages. functional block diagram cs + ? + ? + ? ref gen 100 m v under v oltage 8 .6 v error amplifier v cc + v i n 4.6 v 23a locko u t v ref ? v i n - v i n limit + ? 4 3 7 16 1 14 56 11 10 s ub strate + ? 1.0 - 2.0 v 600 m v p w m i max p u lse skip n i ss/e n ? + + ? e n + ? 2 r s q sy n c (si9119) 12 max 13 15 dr 8 c osc 9 r osc 9.3 v ( v reg ) osc
www.vishay.com 2 document number: 70815 s11-0975?rev. e, 16-may-11 vishay siliconix si9118, si9119 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes: a. device mounted with all leads soldered or welded to pc board. b. derate 7.2 mw/c above 25 c. * exposure to absolute maximum rating conditi ons for extended periods may affect device reliability. stresses above absolute maxi mum rating may cause permanent damage. functional operat ion at conditions other than the operating conditions specified is not implied. on ly one absolute maximum rating should be applied at any one time. absolute maximum ratings (t a = 25 c, unless otherwise noted) parameter symbol limit unit voltage reference v cc to v in 18 v +v in ( note: v cc < + v in + 0.3 v) 200 logic input (sync) - 0.3 to v cc + 0.3 linear input (fb, i cs , i limit , ss/en) - 0.3 to v cc + 0.3 hv pre-regulator input current (continuous) 5 ma storage temperature - 65 to 150 c operating temperature - 40 to 85 d max 3.2 v junction temperature (t j ) 150 c power dissipation (package) a 16-pin soic (y suffix) b 900 mw thermal impedance ( ? ja ) 16-pin soic 140 c/w recommended operating range parameter limit unit voltage reference v cc to v in 10 to 16.5 v +v in 10 to 200 f osc 40 khz to 1 mhz r osc 56 k ? to 1 m ? c osc 47 to 200 pf linear inputs 0 to v cc - 4 v digital inputs 0 to v cc v specifications parameter symbol test conditions unless otherwise specified - v in = 0 v, v cc = 10 v limits d suffix - 40 to 85 c unit temp. a min. typ. b max. reference output voltage v ref osc disabled, t a = 25 c room 3.94 4.0 4.06 v osc disabled, over voltage and temperature ranges c full 3.88 4.0 4.12 short circuit current i sref v ref = -v in - 30 - 5 ma load regulation ? v r / ? i r i ref = 0 to - 1ma 10 40 mv
document number: 70815 s11-0975?rev. e, 16-may-11 www.vishay.com 3 vishay siliconix si9118, si9119 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 parameter symbol test conditions unless otherwise specified - v in = 0 v, v cc = 10 v limits d suffix - 40 to 85 c unit temp. a min. typ. b max. oscillator initial accuracy d f osc r osc = 374 k ?? c osc = 200 pf 90 100 110 khz f osc c r osc = 70 k ?? c osc = 200 pf 450 500 550 voltage stability c ? f/f r osc = 70 k ?? c osc = 200 pf ? f/f = [f(16.5 v) - f(9.5 v)] / f(9.5 v) 12% temperature coefficient c osc tc - 40 ? ? t a ?? 85 c, f osc = 100 khz 200 500 ppm/c sync high pulse width (si9119) 200 ns sync low pulse width (si9119) 200 sync rise/fall time (si9119) 200 sync logic low (si9119) v il 0.8 v sync logic high (si9119) v ih 4 sync range c (si9119) f ext 1.05 x f osc khz pwm/psm pwm/psm logic high v ih 4 v pwm/psm logic low v il 0.8 d max accuracy f osc = 100 khz with 1 % resistor 10 % error amplifier (osc disabled) input bias current i fb v fb = 5 v, ni = v ref < 1.0 200 na input offset voltage v os2 5 25 mv open loop voltage gain c a vol 65 80 db unity gain bandwidth c bw 1.8 2.7 mhz output current i out source (v fb = 3.5 v, ni = v ref ) - 1.0 - 2.7 ma sink (v fb = 4.5 v, ni = v ref ) 1.0 2.4 power supply rejection psrr 10 v ?? v cc ? 16.5 v 50 80 db pre-regulator/start-up input voltage c +v in i in = 10 a room 200 v input leakage current +i in v cc ?? 10 v room 10 a pre-regulator start-up current i start pulse width ?? 300 s, v cc = v ulvo room 8 15 ma v cc pre-regulator turn-off threshold voltage v reg i pre_regulator = 15 a room 8.7 9.3 9.8 v undervoltage lockout v uvlo room 8.0 8.6 9.3 v reg - v uvlo v delta room 0.3 0.7 supply supply current i cc c load ?? 50 pf, f osc = 100 khz 1.9 3.0 ma specifications
www.vishay.com 4 document number: 70815 s11-0975?rev. e, 16-may-11 vishay siliconix si9118, si9119 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes: a. room = 25 c, full = as determin ed by the operating temperature suffix. b. typical values are for design aid only, not guaranteed nor subject to production testing. c. guaranteed by design, not subject to production test. d. c stray ? 5 pf on c osc stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. timing waveforms parameter symbol test conditions unless otherwise specified - v in = 0 v, v cc = 10 v limits d suffix - 40 to 85 c unit temp. a min. typ. b max. protection current limit treshold voltage v i(limit) v fb = 0, ni = v ref 0.5 0.6 0.7 v current limit delay to output c t d v sense 0.85 v, see figure 1 77 100 ns soft-start current i ss - 12 - 23 - 30 a output inhibit voltage v ss(off) soft-start voltage to disable driver output 0.5 1.26 v pulse skipping threshold voltage v ps 80 100 120 mv mosfet driver output high voltage v oh i out = - 10 ma room full v cc - 0.3 v cc - 0.5 v output low voltage v ol i out = 10 ma room full 0.3 0.5 output resistance c r out i out = 10 ma, source or sink room full 20 25 30 50 ? rise time c t r c l = 500 pf room 40 75 ns fall time c t r room 40 75 specifications figure 1. 90 % 0. 8 5 50 % 0 t d t r 10 ns v cc 0 c u rrent sense o u tp u t
document number: 70815 s11-0975?rev. e, 16-may-11 www.vishay.com 5 vishay siliconix si9118, si9119 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (t a = 25 c, unless noted) oscillator frequency supply current vs. output frequency ) z h k ( f t u o 2 x 1000 10 2 x 100 2 x 10 100 1000 47 pf 200 pf 100 pf 150 pf n ote: these c u r v es w ere meas u red in a b oard w ith 3.5 pf of external parasitic capacitance. r osc ? oscillator resistance (k ) ) a m ( t n e r r u c y l p p u s ? i c c f out ? o u tp u t fre qu ency (khz) 36 0 200 400 600 8 00 1000 2 8 20 12 4 0 32 24 16 8 c l = 2500 pf c l = 1000 pf c l = 0 pf v cc = 12 v c osc = 47 pf output driver rise and fall time supply current vs. supply voltage ) s n ( e m i t l l a f d n a e s i r t u p t u o v cc ? s u pply v oltage ( v ) 0 9 10111213141516 50 100 150 200 t r for c l = 2500 pf t f for c l = 2500 pf 17 t r for c l = 1000 pf t f for c l = 1000 pf t r 10 % to 90 % t f 90 % to 10 % v cc ? s u pply v oltage ( v ) ) a m ( t n e r r u c y l p p u s ? i c c 0 9 10111213141516 3 6 9 12 17 r osc = 127 k c osc = 47 pf fs = 500 khz c l = 1000 pf c l = 0 pf switching frequency vs. supply voltage ) z h m ( y c n e u q e r f g n i h c t i w s v cc ? s u pply v oltage ( v ) 8 9 10111213141516 0. 8 5 0.90 1.00 1.05 17 0.95 r osc = 56 k c osc = 100 pf
www.vishay.com 6 document number: 70815 s11-0975?rev. e, 16-may-11 vishay siliconix si9118, si9119 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 pin configurations and ordering information ordering information part number temperature range package si9118dy - 40 to 85 c soic-16 si9118dy-t1 si9118dy-t1-e3 si9119dy SI9119DY-T1 SI9119DY-T1-e3 pin description pin number symbol description 1 +v in input bus voltage ranging from 10 v to 200 v. 2 pwm/psm connected to v ref forces the converter into pwm mode. connected to -v in forces the converter into psm mode. 3 v ref 4 v reference voltage. decouple with 0.1 f ceramic capacitor. 4 ni non-inverting input of an error amplifier. 5 fb inverting input of an error amplifier. 6 comp error amplifier output for external compensation network. 7 ss/en programmable soft-start with external capacitor or externally controlled disable mode. 8 c osc external capacitor to determine the switching frequency. 9 r osc external resistor to determine the switching frequency. 10 i limit pulse by pulse peak current limiting pin. when the current sense voltage ex ceeds the current limit threshold, the gate drive signal is terminated. i limit is also used to sense the cu rrent in pulse skipping mode. 11 i cs current sense input to control feedback response. 12 sync or v sc si9118: slope compensation pin. si9119: cl ock synchronization pin. logic high to low transition from external signal synchronizes the internal clock frequency. 13 d max sets the maximum duty cycle. internally, the maximum duty cycle is clamped to 80 %. 14 -v in single point ground. 15 d r gate drive for the external mosfet switch. 16 v cc supply voltage for the ic after the startup transition. soic si911 8 dy 13 14 15 16 2 3 4 1 10 11 12 5 6 7 9 8 top v ie w + v i n v cc i limit i cs v ref dr n i - v i n fb comp ss/e n v sc c osc r osc d max p w m/psm soic si9119dy 13 14 15 16 2 3 4 1 10 11 12 5 6 7 9 8 top v ie w + v i n v cc i limit i cs v ref dr n i - v i n fb comp ss/e n sy n c c osc r osc d max p w m/psm
document number: 70815 s11-0975?rev. e, 16-may-11 www.vishay.com 7 vishay siliconix si9118, si9119 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 standard application circuits figure 2. si9118 15 w forward converter schematic - 4 8 v (- 42 to - 56 v ) + v i n p w m/psm v ref n i fb comp ss/e n v cc i cs dr - v i n d max tl431 si9420dy i limit c osc r osc v sc v o figure 3. si9119 forward converter with external slope compensation - 4 8 v (- 42 to - 56 v ) + v i n p w m/psm v ref n i fb comp ss/e n v cc i cs dr - v i n d max i limit c osc r osc sy n c si9420dy tl431
www.vishay.com 8 document number: 70815 s11-0975?rev. e, 16-may-11 vishay siliconix si9118, si9119 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 detailed operational description start-up si9118/si9119 are designed with internal depletion mode mosfet capable of powering directly from the high input bus voltage. this feature eliminates the typical external start-up circuit saving valuable space and cost. but, most of all, this feature improves the converter efficiency during full load and has an even greater impact on light load. with an input bus voltage applied to the +v in pin, the v cc voltage is regulated to 9.3 v. the uvlo circuit prevents the controller output driver section from turning on, until v cc voltage exceeds 8.7 v. in order to maximize converter efficiency, the designer should provide an external bootstrap winding to override the internal v cc regulator. if external vcc voltage is greater than 9.3 v, the internal depletion mode mosfet regulator is disabled and power is derived from the external v cc supply. the v cc supply provides power to the internal circuity as well as providing supply voltage to the gate drive circuit. soft-start/enable the soft-start time is ex ternally prog rammable with capacitor connected to the ss/en pin. a constant current source provides the current to the ss/en pin to generate a linear start-up time versus the capacitance value. the ss/en pin clamps the error amplifier output voltage, limiting the rate of increase in duty cycle. by controlling the rate of rise in duty cycle gradually, the output voltage rises gradually preventing the output voltage from overshooting. the ss/en pin can also be used to enable or disable the output driver section with an external logic signal. synchronization the synchronization to external clock is easily accomplished by connecting the external clock into the sync pin (si9119 only). the logic high to low transition synchronizes the clock. the external clock frequency must be at least 5 % faster than the internal clock frequency. reference voltage the reference voltage for the si9118/si9119 are set at 4.0 v. the reference voltage is not connected to the non-inverting inputs of the error amplifier, therefore, the minimum output voltage is not limited to reference voltage. the v ref pin requires a 0.1 f decoupling capacitor. error amplifier the error amplifier gain-ban dwidth product is critical parameter which determines the transient response of converter. the transient response is function of both small and large signal re sponses. the small signal response is determined by the feedback compensation network while the large signal response is determined by the inductor di/dt slew rate. besides the inductance value, the error amplifier gain-bandwidth determine the converter response time. in order to minimize the response time, si9118/si9119 is designed with a 2.7 mhz error amplifier gain-bandwidth product to provide the widest converter bandwidth possible. pwm mode the converter operates in pwm mode if the pwm/ psm pin is connected to v ref pin or logic high. as the load current and line voltage vary, the si9118/si9119 maintain constant switching frequency until they reach minimum duty cycle. once the output voltage regulation is exceeded with minimum duty cycle, the switching frequency will cont inue to decrease until regulation is achieved. the switching frequency is controlled by the external r osc and c osc as shown by the typical oscillator frequency curve. in pwm mode, output ripple noise is constant reducing emi concerns as well as simplifying the filter to minimize the system noise. pulse skipping mode if the pwm/psm pin is connected to -v in pin (logic low), the converter can operate in either pwm or psm mode depending on the load current. the converter automatically transitions from pwm to psm or vise versa to maintain output voltage regulation. in psm mode, the mosfet switch is turned on until the peak current sensed voltage reaches 100 mv and the output voltage meets or exceeds its regulation voltage. the converter is operating in pulse skipping mode because each pulse delivers excess energy into the output capacitor forcing the output voltage to exceed its regulation voltage. by forcing the output voltage to exceed the regulation voltage, succeeding pulses are skipped until the output voltage drops below the regulation point. therefor e, switching frequency will continue to reduce during psm control as the demand for output current decreases. the pulse skipping mode cuts down the switching losses, the dominant power consumed during low output current, thereby maintaining high efficiency throughout the entire load range. with pwm/psm pin in logic low state, the converter transitions back into pwm mode, if the peak current sensed voltage of 100 mv does not generate the required output voltage. in the region between pulse skipping mode and pwm mode, the controller may transition between the two modes, delivering spurts of pulses. this may cause the current waveform to look irregular, but this will not overly affect the ripple voltage. even in this transitional mode, efficiency remains high.
document number: 70815 s11-0975?rev. e, 16-may-11 www.vishay.com 9 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 vishay siliconix si9118, si9119 detailed operational description (cont?d) programmable duty cycle control the maximum duty cycle limit is controlled by the voltage on d max pin. a d max voltage of 3.2 v generates 80 % duty cycle while 0.0 v generates 0 % duty cycle. the 80 % duty cycle is maximum default condition at 1 mhz switching frequency. the d max voltage can be easily generated using resistor divider from the reference voltage.the maximum duty cycle limitation will be differ ent when the converter is synchronized by an external frequency. if the internal free running frequency is much slower than the external sync signal (sync signal causes the internal clock to reset be fore the cosc voltage ramps to 3.2 v) , duty cycle is determined by the one shot discharge time of the osc illator capacitor (100 ns). therefore, with 1 mhz sync signal, maximum duty cycle of 90 % can be achieved (100 ns is 10 % of 1 mhz). if the internal free running frequency is very close to the external sync frequency (sync signal causes the internal clock to reset somewhere between 3.2 v to 4 v), duty cycle is determined by the ratio of c osc voltage at the sync point and the 3.2 v. at this condition, the maximum duty cycle can be greater than 90 %. therefore, d max voltage must be modified in order to maintain desired maximum duty cycle. slope compensation slope compensation is necessary for duty cycles greater than 50 % to stabilize the inner current loop and maintain overall loop st ability. in orde r to simplify the slope compensation circuitry, the si9118 provides the buffered oscillator ramp signal, v sc to be used for external slope compensation. v sc is only available when dr is high. the v sc signal super-imposed with actual current sense signal should be used by the pwm comparator to determine the duty cycle. the summation of this signal should be fed into i cs pin. for optimum performance, proper slope compensation is required. the amount of slope compensation is determined by the resistors connected to the i cs pin. the amplitude of the v sc signal is same as the c osc pin voltage ( ?? 4 v). for designs which use with sync pin, instead of v sc pin, the converter can still operate at duty cycles greater than 50 % by generating an external slope compensation ramp using a simple rc circuit from the mosfet driver output pin as shown on the application circuit. over current protection si9118/si9119 are designed with a pulse-to-pulse peak current limiting protection circuit to protect itself, and the load in case of a failure. the voltage across the sense resistor is monitore d continuously and if the voltage reaches its trigger level, the duty cycle is terminated. this limits the maximum current delivered to the load. in order to improve the accuracy of over current protection from traditional controllers, si9118/ si9119 are designed with separate i limit and i cs pins. voltage on the i limit pin does not sum in the traditional slope compensation voltage, which adds error into the detection level. i cs pin is used to sum the current sense signal and the slope compensation for loop stability. output driver stage the dr pin is designed to drive a low-side n-channel mosfet. the driver stage is sized to sink and source peak currents up to 500 ma with v cc = 12 v. this provides ample drive capab ility for 50 w of output power. vishay siliconix maintains worldwide manufacturing capability. pro ducts may be manufactured at on e of several qualified locatio ns. reliability data for silicon tech- nology and package reliability represent a composite of all qua lified locations. for related documents such as package/tape dra wings, part marking, and reliability data, see www.vishay.com/ppg?70815 .
all leads 0.101 mm 0.004 in e h c d e b a1 l 4 3 12 8 7 56 13 14 16 15 9 10 12 11 package information vishay siliconix document number: 72807 28-jan-04 www.vishay.com 1 soic (narrow): 16-lead (power ic only) jedec part number: ms-012 millimeters inches dim min max min max a 1.35 1.75 0.053 0.069 a 1 0.10 0.20 0.004 0.008 b 0.38 0.51 0.015 0.020 c 0.18 0.23 0.007 0.009 d 9.80 10.00 0.385 0.393 e 3.80 4.00 0.149 0.157 e 1.27 bsc 0.050 bsc h 5.80 6.20 0.228 0.244 l 0.50 0.93 0.020 0.037 0 8 0 8 ecn: s-40080?rev. a, 02-feb-04 dwg: 5912
document number: 91 000 www.vishay.com revision: 11-mar-11 1 disclaimer legal disclaimer notice vishay all product, product specifications and data ar e subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectivel y, vishay), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicab le law, vishay disc laims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, incl uding without limitation specia l, consequential or incidental dama ges, and (iii) any and all impl ied warranties, including warran ties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of pro ducts for certain types of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in gene ric applications. such statements are not binding statements about the suitability of products for a partic ular application. it is the customers responsibility to validate that a particu lar product with the properties described in th e product specification is su itable for use in a particul ar application. parameters provided in datasheets an d/or specifications may vary in different applications and perfo rmance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vishays term s and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vishay product co uld result in person al injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk and agr ee to fully indemnify and hold vishay and it s distributors harmless from and against an y and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that vis hay or its distributor was negligent regarding the design or manufact ure of the part. please contact authorized vishay personnel t o obtain written terms and conditions regarding products designed fo r such applications. no license, express or implied, by estoppel or otherwise, to any intelle ctual property rights is gran ted by this document or by any conduct of vishay. product names and markings noted herein may be trademarks of their respective owners.

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